![]() ![]() ![]() For the first time, we have formulated the generalized equations to perform the quantitative analysis of the required resources (number of nanomagnets (NM), majority gates (MG) and clock cycles (CC)) for higher bit adder architecture implementation. ![]() With reference to the Table IV, we have formulated the generalized equations (6),(6a),(6b) for computing the required number of nanomagnets (NM), majority gates (MG) and clock cycles (CC) respectively for the implementation of nanomagnetic adder as follows: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A c c e p t e d M a n u s c r i p t, 5565, 4797, 3773 MGs: 1024, 768, 1024, 768 & CCs: 2048, 1024, 2048, 1024 depending on the design opted as tabulated in Table IV In a nutshell, this is the first of its kind computational modeling and simulation based demonstration of the runtime re-reconfigurability of the accurate adder using two serially connected majority gates resulting significant improvement in the area efficiency (∼86 % reduction in the number of nanomagnets) and speed (∼ 83 % & ∼ 93 % reduction in the number of majority gates and clock cycles respectively) Consequently, the on-chip clocking schematic for the proposed RRN adder implementation for both horizontal and vertical layouts are introduced for the first time to the best of authors' knowledge. The performance comparison parameters of the proposed RRN adder with the state of art is tabulated in Table IV along with the quantitative analysis of the higher bit adder and the corresponding percentage reduction shown in Fig. All the logic variations of the adder can therefore be achieved using one design layout (reconfigured in runtime) with different applied H Clock as shown in Fig. ![]()
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